project:ledum:start
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| project:ledum:start [2025/04/25 13:13] – [Streaming Setup in Brmlab] joe | project:ledum:start [2025/05/05 19:50] (current) – verilog based SOC GUI tma | ||
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| As a proof-of-concept an assembly language compiler and IDE support was implemented for a very simple Harvard architecture 8-bit CPU. A graphical emulator for the same simple CPU was created as well. The aim of these tooling efforts is to provide a unified framework for creating custom instruction sets including their assemblers and emulators. | As a proof-of-concept an assembly language compiler and IDE support was implemented for a very simple Harvard architecture 8-bit CPU. A graphical emulator for the same simple CPU was created as well. The aim of these tooling efforts is to provide a unified framework for creating custom instruction sets including their assemblers and emulators. | ||
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| + | <WRAP clear></ | ||
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| + | ==== Simulator GUI ==== | ||
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| + | {{ : | ||
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| + | A simple GUI was developed for simulating a SOC written in Verilog. | ||
| <WRAP clear></ | <WRAP clear></ | ||
project/ledum/start.txt · Last modified: 2025/05/05 19:50 by tma