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founder: tlapka
depends on:
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~~META: status = idea &relation firstimage = :project:brmcarramba.png ~~

LowCost multiprocessor cluster based on cheap ARM MCU Cortex - M3 (in phase 1.)

Goals of this project

  • Create low-cost multiprocessor computing device based on cheap ARM cpu ( LPC )
  • Learn about multiprocessors device desing


Device will contains slaveNodes, masterNode, storageNodes, this device is superNode, this superNode contains:

  • slaveNodes - processors card
  • masterNode - controller for internal communication between slaveNodes and external communication between superNodes
  • storageNodes - card what have n. SD cards slots for storage, or SATA interfaces

slaveNode concept

each slaveNode have communication core and computing cores. Computing cores have one shared internal bus and access to dual port RAM. On other side DPRAM is communication core. This design allow use multiple design inside of slaveNode, cuz slaveNode is represented in superNode's internal bus by communication core. Then we can put on the slaveNode n. computing cores and doesn't matter if slaveNode have 4 computing cores or 128 cores or if computing cores have different architecture.

masterNode concept

masterNode is main controller for data interchange between slaveNodes (and superNodes, probably by ethernet interface (in future)).

Phases of project

Step #1

One slaveNode board have 8 computing ARMs LPC1343 and 1 communication core (same MCU). brmCarraba (superNode) have 6 this boards and 1 masterNode. Master node have 1 core with ehternet interface. masterNode control internal bus between nodes, ethernet output (for connecting superNodes), USB port, VGA output, port for handling small OLED dislay on case (enclosure), PS/2 keyboard. USB can be in HOST mode.

ARM Cortex-M3 aka LPC1343


  • 72MHz
  • 32 kB on-chip flash programming memory.
  • 8 kB SRAM.
  • 42 General Purpose I/O (GPIO)
  • integrated oscillator with an operating range of 1 MHz to 25 MHz
  • Serial interfaces:
    • USB 2.0 full-speed device controller with on-chip PHY for device
    • UART with fractional baud rate generation, modem, internal FIFO, and RS-485/EIA-485 support
    • SSP controller with FIFO and multi-protocol capabilities
    • Additional SSP controller
    • I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode
  • Four general purpose counter/timers
  • GPIO pins can be used as edge and level sensitive interrupt sources
  • Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz
  • Power-On Reset
Case for brmCarramba

i choose al box what have profile inside, cuz i will put in this box card like slaveNode and masterNode .. this box can contains 11 pcb. Now i can desing PCB cuz i know real allowed sice of this PCB. Size is 20x103x53mm.

  • 1455N1202BK HAMMOND - case


Part List - [not finish yet]
No.descriptiondatasheetone piece pricesum
55x LPC1343FBD48,151 - MCU, 32BIT, CORTEX M3, 48LQFPLPC1343.pdf 60.39Kc 3321,45Kc
1xDAVICOM - DM9102DEP - IC, ENET CNTRL, 10/100M PHY, 128LQFPDM9102DEP.pdf143.84Kc143.84Kc
8x stabilizator 3,3V LT1117CST-3.3#PBF. - IC, LDO VOLT REG, 3.3V, 0.8A LT1117CST.pdf 110.78Kc 886,24Kc
Sum 4351,53Kc


project/brmcarramba/start.txt · Last modified: 2016/11/28 02:45 by ruza