Ledum
founder:	Yokotashi
depends on:
interested:	abyssal bluebear ccx hexo joe prilezitostnypetr RAINBOF sachy santiago tma
software license:
hardware license:

This project aims to design and develop a new central processing unit (CPU) with a primary focus on correctness and object capabilities. The design will prioritize formal verification techniques, ensuring the CPU’s functional correctness while introducing innovative approaches to resource management using object capabilities for improved security, efficiency, and modularity.

1. Achieve High Correctness in Design:
   • Use formal methods, simulation, and rigorous testing to verify that the CPU’s architecture is functionally correct.
   • Ensure that the CPU meets or exceeds industry standards for reliability and precision.
2. Implement Object Capabilities Model:
   • Integrate an object capabilities model into the CPU’s architecture to allow fine-grained, secure management of memory and I/O resources.
   • Ensure that resource access control is embedded at the hardware level to improve security by default.
3. Enable Scalable Security Mechanisms:
   • Design the CPU with scalable security features, leveraging capabilities to prevent unauthorized access and misuse of system resources.
   • Provide users with the flexibility to define and manage their own access control policies through object capabilities.
4. Optimize Performance:
   • Ensure that the CPU achieves optimal performance in terms of throughput, latency, and power consumption, without compromising correctness or security.
   • Ensure, that the CPU architecture can be parallelized to achieve IPC>1 including OoO execution, although to do so isn't primary objective.
   • Balance hardware features for high-performance tasks with robust security measures for sensitive operations.
5. Establish Robust Ecosystem Support:
   • Develop comprehensive software toolchains and drivers to support the object capability model.
   • Collaborate with industry partners to ensure broad compatibility with existing operating systems and applications.

• CPU Architecture Design: Define instruction sets, pipeline architecture, memory hierarchy, and integration of object capabilities.
• Formal Verification: Apply formal methods to mathematically prove the correctness of critical parts of the architecture.
• Security & Resource Management: Implement object capabilities as a mechanism to control access to system resources.
• Prototyping and Simulation: Build prototypes and simulate the architecture to validate design decisions.
• Performance Evaluation: Benchmark the new CPU's performance across several applications to assess trade-offs between correctness, performance, and security.
• Software Toolchain Development: Develop and release supporting software tools, such as compilers, debuggers, and simulators, that work with the new object capability model.

• Development of end-user software applications or operating systems.
• Manufacturing of physical CPU chips (to be handled post-design phase).
• Integration into mass-market consumer devices (focus will be on specialized, high-assurance markets initially).

As a part of our efforts, we have realized that different members of the team have different experience with various scientific and engineering fields and it would be very helpful to ensure that everyone has some basic understanding of all required topics. The workshops typically take place during the working group's regular meetings on Thursdays (see Events).

If there is enough interest, we are streaming the workshops online using https://meet.jit.si/. We are also trying to get our A/V streaming and editing skills to a level that allows for publishing the recordings of the workshops. Any help with such endeavor would be more than welcome.

• 2024-10-10 16:00 tma - Verilog I: Introduction to Verilog (CZ)
• 2024-10-24 16:00 tma - Verilog II: Register Bank in Verliog (CZ)
• 2024-10-31 16:00 joe - Lambda Calculus I: Introduction to Lambda Calculus (CZ)
• 2024-11-07 18:00 tma - Verilog III: Advanced Verilog (CZ)
• 2024-11-14 16:00 sachy - Assembler on Mainframes (CZ)
• 2024-11-21 18:00 Yokotashi - Introduction to Electronics (CZ)
• 2024-11-28 16:00 tma - Verilog IV: Testbenches (CZ)
• 2024-12-05 16:00 joe - Lambda Calculus II: Lexical Scoping and Evaluator Implementation (CZ)
• 2024-12-12 16:00 ccx – History of Capability Systems I (CZ)
• 2025-01-09 17:00 hexo – Adders and Multipliers (CZ/SK)

Warning: This part may change wildly at this stage.

• 64 GPR
• upto 64 PTR (Pointer registers)
• special registers (CS:IP and several configuration registers probably)
• - No flag register (flags are going either to another GPR or to a special 4-bits adjacent to every GPR), this should help future with parallelization

• Fat Pointers supported and tested by HW
• Ultra Fat Pointers supported and tested by HW, can't be dereferenced outside the CS stored inside them

• All RAM and registers is tagged, so ALU knows which type it's operating on and pointer cannot be created freely
• Types: int, uint, float in 4, 8 … 64 bit lengths fit in vector 64-bit long; Fat pointer, Ultra fat pointer

As a proof-of-concept an assembly language compiler and IDE support was implemented for a very simple Harvard architecture 8-bit CPU. A graphical emulator for the same simple CPU was created as well. The aim of these tooling efforts is to provide a unified framework for creating custom instruction sets including their assemblers and emulators.

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