We will demonstrate how FPGA clusters dedicated to cracking ciphers are designed. We will start with a simple slow DES core that takes 19 cycles for one operation and show how to turn in into pipelined implementation that has throughput of one encryption per cycle while still keeping high clock rate.

EFF DES Cracker

recording: http://nat.brmlab.cz/talks/2013-12-09-fpga-des-cracking.mkv