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Custom chip made for Vaisala by VLSI solution.




  • verify memory sizes
    • detect memory types (RAM/EEPROM/registers/???)
  • try detect building blocks (ALU, registers, whatever)
  • create large scale image of deccaped chip
  • create large scale image of bottom layers of decappend chip
  • find out pinouts
  • try dump with JTAG (could be easilly found by brute-force)
  • reverse chip structure/schematic


chip organization schema:

       /-  *************
widht ---  *************   -\
       \-  *************     \
           =============      |- rows
           *************     /
           *************   -/
  • width: number of bite strings per row, should be the same as bus width (or smaller)
  • cols: ussualy the largest side of memory array, orthogonal to bus
  • rows: one row is composed from strings of bits, each row contains 'cols'x'width' bits

Memory regions have characteristic structure, it is usually grid.

Chip was deccaped and the following memory regions were found by microscoping the chip.

size name oranization description
64kb / 8kB RAM1 rows: 16, cols: 256, width: 32 probably RAM ?
256b / 32B EEPROM2 rows: 4, cols: 64, width: 8 this might be organized just 64×64 bit
2048b / 256B ROM3 rows: 8, cols: 128, width: 16 organization might be 32x4x128
512b / 64B ROM4 rows: 8, cols: 64, width: 8 ???
192b / 24B ROM5 rows: 8, cols: 96, width 16 ???

Work in progress in getting high-resolution digital images of the chip from our microscope.

there is one more region which looks like memory, this contains probably registers.

(name is just name, the type of memory is not known)


Deccaped chip - low resolution. Credit: Klepko

deccaped chip - low resolution. Credit: Klepko

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