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LowCost multiprocessor cluster based on cheap ARM MCU Cortex - M3 (in phase 1.)
Device will contains slaveNodes, masterNode, storageNodes, this device is superNode, this superNode contains:
each slaveNode have communication core and computing cores. Computing cores have one shared internal bus and access to dual port RAM. On other side DPRAM is communication core. This design allow use multiple design inside of slaveNode, cuz slaveNode is represented in superNode's internal bus by communication core. Then we can put on the slaveNode n. computing cores and doesn't matter if slaveNode have 4 computing cores or 128 cores or if computing cores have different architecture.
masterNode is main controller for data interchange between slaveNodes (and superNodes, probably by ethernet interface (in future)).
One slaveNode board have 8 computing ARMs LPC1343 and 1 communication core (same MCU). brmCarraba (superNode) have 6 this boards and 1 masterNode. Master node have 1 core with ehternet interface. masterNode control internal bus between nodes, ethernet output (for connecting superNodes), USB port, VGA output, port for handling small OLED dislay on case (enclosure), PS/2 keyboard. USB can be in HOST mode.
i choose al box what have profile inside, cuz i will put in this box card like slaveNode and masterNode .. this box can contains 11 pcb. Now i can desing PCB cuz i know real allowed sice of this PCB. Size is 20x103x53mm.
|No.||description||datasheet||one piece price||sum|
|55x||LPC1343FBD48,151 - MCU, 32BIT, CORTEX M3, 48LQFP||LPC1343.pdf||60.39Kc||3321,45Kc|
|1x||DAVICOM - DM9102DEP - IC, ENET CNTRL, 10/100M PHY, 128LQFP||DM9102DEP.pdf||143.84Kc||143.84Kc|
|8x||stabilizator 3,3V LT1117CST-3.3#PBF. - IC, LDO VOLT REG, 3.3V, 0.8A||LT1117CST.pdf||110.78Kc||886,24Kc|